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FDS2582
September 2002
FDS2582
N-Channel PowerTrench(R) MOSFET 150V, 4.1A, 66m
Features
* r DS(ON) = 57m (Typ.), VGS = 10V, ID = 4.1A * Qg(tot) = 19nC (Typ.), VGS = 10V * Low Miller Charge * Low QRR Body Diode * Optimized efficiency at high frequencies * UIS Capability (Single Pulse and Repetitive Pulse)
Applications
* DC/DC converters and Off-Line UPS * Distributed Power Architectures and VRMs * Primary Switch for 24V and 48V Systems * High Voltage Synchronous Rectifier * Direct Injection / Diesel Injection Systems * 42V Automotive Load Control
Formerly developmental type 82855
* Electronic Valve Train Systems
Branding Dash
5
5
4 3 2 1
6 7
1 2 3 4
8
MOSFET Maximum Ratings TA = 25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID Continuous (TA = 25oC, VGS = 10V, R JA = 50oC/W) Continuous (TA = 100 C, VGS = 10V, RJA = 50 C/W) Pulsed E AS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature
o o
SO-8
Ratings 150 20 4.1 2.6 Figure 4 252 2.5 20 -55 to 150
Units V V A A A mJ W mW/oC
o
C
Thermal Characteristics
RJA RJA RJC Thermal Resistance, Junction to Ambient at 10 seconds (Note 3) Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3) Thermal Resistance, Junction to Case (Note 2) 50 80 25
o
C/W C/W
oC/W o
Package Marking and Ordering Information
Device Marking FDS2582 Device FDS2582 Package SO-8 Reel Size 330mm Tape Width 12mm Quantity 2500 units
(c)2002 Fairchild Semiconductor Corporation
FDS2582 Rev. B
FDS2582
Electrical Characteristics TA = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 120V VGS = 0V VGS = 20V TC = 150oC 150 1 250 100 V A nA
On Characteristics
VGS(TH) Gate to Source Threshold Voltage V GS = VDS, ID = 250A ID = 4.1A, VGS = 10V rDS(ON) Drain to Source On Resistance ID = 2A, VGS = 6V ID = 4.1A, VGS = 10V, TC = 150oC 2 0.057 0.065 0.125 4 0.066 0.098 0.146 V
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge VDS = 25V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 2V VDD = 75V ID = 4.1A Ig = 1.0mA 1290 150 32 19 2.3 5.4 3.1 4.4 25 3.0 pF pF pF nC nC nC nC nC
Resistive Switching Characteristics (VGS = 10V)
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 75V, ID = 4.1A VGS = 10V, RGS = 16 11 19 36 26 45 92 ns ns ns ns ns ns
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 4.1A ISD = 2A ISD= 4.1A, dISD/dt= 100A/s ISD= 4.1A, dISD/dt= 100A/s 1.25 1.0 63 116 V V ns nC
Notes: 1: Starting TJ = 25C, L = 56mH, IAS = 3A. 2: RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal referance is defined as the solder mounting surface of the drain pins. R JC is guaranteed by design while RCA is determined by the user's board design. 3: RJA is measured with 1.0 in2 copper on FR-4 board
(c)2002 Fairchild Semiconductor Corporation
FDS2582 Rev. B
FDS2582
Typical Characteristics TA = 25C unless otherwise noted
1.2 POWER DISSIPATION MULTIPLIER 5 VGS = 10V 4 ID, DRAIN CURRENT (A) 0 25 50 75 100 125 150
1.0
0.8
3
0.6
2
0.4
1 0.2 0 25 50 TA , AMBIENT TEMPERATURE (oC) 75 100 125 TC, CASE TEMPERATURE (oC) 150
0
Figure 1. Normalized Power Dissipation vs Ambient Temperature
2 1
Figure 2. Maximum Continuous Drain Current vs Case Temperature
ZJA, NORMALIZED THERMAL IMPEDANCE
0.1
DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM
RJA=50oC/W
0.01 SINGLE PULSE
t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA
0.001 10-5 10 -4 10-3 10-2 10-1 100 t , RECTANGULAR PULSE DURATION (s) 101 102 103
Figure 3. Normalized Maximum Transient Thermal Impedance
400 TA = 25oC FOR TEMPERATURES ABOVE 25o C DERATE PEAK CURRENT AS FOLLOWS: I = I25 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 150 - TC 125
IDM, PEAK CURRENT (A)
100
1
VGS = 10V 10-5 10-4 10-3 10-2 10-1 100 101 102 103
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
(c)2002 Fairchild Semiconductor Corporation
FDS2582 Rev. B
FDS2582
Typical Characteristics TA = 25C unless otherwise noted
100 10s IAS, AVALANCHE CURRENT (A) STARTING TJ = 25oC 7
ID, DRAIN CURRENT (A)
10 100s 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.1 SINGLE PULSE TJ = MAX RATED TC = 25oC
1
STARTING TJ = 150o C
1ms 10ms 100ms
1s 0.1
0.01 0.1 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 400
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100
0.01
Figure 5. Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching Capability
30
30 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A)
TA = 25oC VGS = 10V
25 ID , DRAIN CURRENT (A)
25
20 TJ = 150oC 15 TJ = 10 TJ = -55oC 25oC
20 VGS = 6V
VGS = 7V
15
10
VGS = 5V
5
5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
0 3.5 4.0 4.5 5.0 5.5 VGS , GATE TO SOURCE VOLTAGE (V) 6.0
0 0 0.5 1.0 1.5 VDS , DRAIN TO SOURCE VOLTAGE (V) 2.0
Figure 7. Transfer Characteristics
DRAIN TO SOURCE ON RESISTANCE (m ) 66 VGS = 6V 64 NORMALIZED DRAIN TO SOURCE ON RESISTANCE
Figure 8. Saturation Characteristics
2.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0
62 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
1.5
60
58
VGS = 10V
1.0 VGS = 10V, ID = 4.1A 0.5
56 1.0 1.5 2.0 2.5 3.0 3.5 ID, DRAIN CURRENT (A) 4.0 4.5 -80 -40
0 40 80 120 TJ, JUNCTION TEMPERATURE (o C)
160
Figure 9. Drain to Source On Resistance vs Drain Current
Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature
(c)2002 Fairchild Semiconductor Corporation
FDS2582 Rev. B
FDS2582
Typical Characteristics TA = 25C unless otherwise noted
1.2 VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.2 ID = 250A
NORMALIZED GATE THRESHOLD VOLTAGE
1.0
1.1
0.8
1.0
0.6 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160
0.9 -80 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160
Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature
3000 CISS = CGS + CGD
Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 75V 8
1000 C, CAPACITANCE (pF) COSS CDS + CGD
6
CRSS = CGD 100
4
2
10 0.1
VGS = 0V, f = 1MHz 0 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 150 0 5
WAVEFORMS IN DESCENDING ORDER: ID = 4.1A ID = 2A 10 15 Qg, GATE CHARGE (nC) 20
Figure 13. Capacitance vs Drain to Source Voltage
Figure 14. Gate Charge Waveforms for Constant Gate Currents
(c)2002 Fairchild Semiconductor Corporation
FDS2582 Rev. B
FDS2582
Test Circuits and Waveforms
VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG VDD
+
BVDSS
VDS
VDD
IAS 0.01
0 tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT) VDS
L VGS = 10V VGS
+
VDD DUT Ig(REF) 0 Qg(TH)
VGS VGS = 2V Qgs2 Qgs Ig(REF) 0 Qgd
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
90% VGS 50% PULSE WIDTH 50%
RGS
VGS
0
10%
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
(c)2002 Fairchild Semiconductor Corporation
FDS2582 Rev. B
FDS2582
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
(T -T ) JM A P = -----------------------------DM R JA
maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. R JA = 64 + -------------------------------
26 0.23 + Area
(EQ. 2)
(EQ. 1) The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.
200 RJA = 64 + 26/(0.23+Area)
In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized
150 COPPER BOARD AREA - DESCENDING ORDER 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2
RJA (o C/W)
150
100
50 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) 10
Figure 21. Thermal Resistance vs Mounting Pad Area
ZJA, THERMAL IMPEDANCE (o C/W)
120
90
60
30
0 10-1 10 0 101 t , RECTANGULAR PULSE DURATION (s) 102 103
Figure 22. Thermal Impedance vs Mounting Pad Area
(c)2002 Fairchild Semiconductor Corporation
FDS2582 Rev. B
FDS2582
PSPICE Electrical Model
.SUBCKT FDS2582 2 1 3 ; Ca 12 8 4.5e-10 Cb 15 14 5.0e-10 Cin 6 8 1.25e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 155.5 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 5.61e-9 Ldrain 2 5 1e-9 Lsource 3 7 1.98e-9 RLgate 1 9 56.1 RLdrain 2 5 10 RLsource 3 7 19.8 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 30.0e-3 Rgate 9 20 1.5 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 20.0e-3 Rvthres 22 8 Rvthresmod 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*60),2.5))} .MODEL DbodyMOD D (IS=2.4E-12 N=1.0 RS=10.0e-3 TRS1=2.1e-3 TRS2=4.7e-7 + CJO=9.0e-10 M=0.64 TT=3.9e-8 XTI=4.6) .MODEL DbreakMOD D (RS=1.0 TRS1=1.4e-3 TRS2=-5e-5) .MODEL DplcapMOD D (CJO=2.8e-10 IS=1e-30 N=10 M=0.64) .MODEL MmedMOD NMOS (VTO=3.5 KP=4.0 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.5) .MODEL MstroMOD NMOS (VTO=4.2 KP=50 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=2.92 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=15 RS=0.1) .MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-1.0e-8) .MODEL RdrainMOD RES (TC1=1.15e-2 TC2=3.0e-5) .MODEL RSLCMOD RES (TC1=4.4e-3 TC2=2.9e-6) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-3.9e-3 TC2=-1.6e-5) .MODEL RvtempMOD RES (TC1=-3.5e-3 TC2=1.5e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.0 VOFF=-2.0) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-3.0) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=1.0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.0 VOFF=-1.5) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2002 Fairchild Semiconductor Corporation FDS2582 Rev. B
rev July 2002
LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO CIN LSOURCE 8 RSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT 15 17 RBREAK 18 RVTEMP 19 VBAT + 22 7 RLSOURCE SOURCE 3 21 16 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED 5 DRAIN 2
RSLC2
5 51 ESG + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 6 8 -
+
DBODY
FDS2582
SABER Electrical Model
REV July 2002 template FDS2582 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.4e-12,nl=1.0,rs=10.0e-3,trs1=2.1e-3,trs2=4.7e-7,cjo=9.0e-10,m=0.64,tt=3.9e-8,xti=4.6) dp..model dbreakmod = (rs=1.0,trs1=1.4e-3,trs2=-5e-5) dp..model dplcapmod = (cjo=2.8e-10,isl=10e-30,nl=10,m=0.64) m..model mmedmod = (type=_n,vto=3.5,kp=4.0,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.2,kp=50,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.92,kp=0.04,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-3.0,voff=-2.0) LDRAIN sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-3.0) DPLCAP 5 DRAIN sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=1.0) 2 10 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=1.0,voff=-1.5) RLDRAIN c.ca n12 n8 = 4.5e-10 RSLC1 51 c.cb n15 n14 = 5.0e-10 RSLC2 c.cin n6 n8 = 1.25e-9
ISCL
dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 155.5 spe.eds n14 n8 n5 n8 = 1 GATE spe.egs n13 n8 n6 n8 = 1 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 5.61e-9 l.ldrain n2 n5 = 1e-9 l.lsource n3 n7 = 1.98e-9 res.rlgate n1 n9 = 56.1 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 19.8
CA LGATE
ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8
50 RDRAIN 21 16
DBREAK 11 DBODY MWEAK MMED EBREAK + 17 18 -
RLGATE CIN
MSTRO 8
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE S1A 12 S1B 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-1.0e-8 res.rdrain n50 n16 = 30.0e-3, tc1=1.15e-2,tc2=3.0e-5 res.rgate n9 n20 = 1.5 res.rslc1 n5 n51 = 1e-6, tc1=4.4e-3,tc2=2.9e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 20.0e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-3.9e-3,tc2=-1.6e-5 res.rvtemp n18 n19 = 1, tc1=-3.5e-3,tc2=1.5e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/60))** 2.5)) }
(c)2002 Fairchild Semiconductor Corporation
FDS2582 Rev. B
FDS2582
SPICE Thermal Model
REV July 2002 FDS2582 Copper Area =1.0 in2 CTHERM1 TH 8 4e-4 CTHERM2 8 7 5e-3 CTHERM3 7 6 6e-2 CTHERM4 6 5 9e-2 CTHERM5 5 4 3e-1 CTHERM6 4 3 4e-1 CTHERM7 3 2 9e-1 CTHERM8 2 TL 2 RTHERM1 TH 8 5e-1 RTHERM2 8 7 6e-1 RTHERM3 7 6 4 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 9 RTHERM7 3 2 15 RTHERM8 2 TL 23
th
JUNCTION
RTHERM1
CTHERM1
8
RTHERM2
CTHERM2
7
RTHERM3
CTHERM3
6
SABER Thermal Model
Copper Area = 1.0 in template thermal_model th tl thermal_c th, tl { CTHERM1 TH 8 4e-4 CTHERM2 8 7 5e-3 CTHERM3 7 6 6e-2 CTHERM4 6 5 9e-2 CTHERM5 5 4 3e-1 CTHERM6 4 3 4e-1 CTHERM7 3 2 9e-1 CTHERM8 2 TL 2 RTHERM1 TH 8 5e-1 RTHERM2 8 7 6e-1 RTHERM3 7 6 4 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 9 RTHERM7 3 2 15 RTHERM8 2 TL 23 }
2
RTHERM4
CTHERM4
5
RTHERM5
CTHERM5
4
RTHERM6
CTHERM6
3
RTHERM7
CTHERM7
2
RTHERM8
CTHERM8
tl
CASE
TABLE 1. THERMAL MODELS COMPONANT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.04 in2 3.2e-1 8.5e-1 0.3 24 36 53 0.28 in2 3.5e-1 9.0e-1 1.8 18 21 37 0.52 in2 4.0e-1 9.0e-1 2.0 12 18 30 0.76 in2 4.0e-1 9.0e-1 2.0 10 16 28 1.0 in2 4.0e-1 9.0e-1 2.0 9 15 23
(c)2002 Fairchild Semiconductor Corporation
FDS2582 Rev. B
TRADEMARKS
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LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. I1

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